Architecting fast and energy-efficient hardware accelerators for emerging ML workloads using hardware-software co-design

dc.contributor.advisor	Mekie, Joycee
dc.contributor.author	Issac, Tom Glint
dc.date.accessioned	2024-09-13T08:19:24Z
dc.date.available	2024-09-13T08:19:24Z
dc.date.issued	2024
dc.identifier.citation	Issac, Tom Glint (2024). Architecting fast and energy-efficient hardware accelerators for emerging ML workloads using hardware-software co-design. Gandhinagar: Indian Institute of Technology Gandhinagar, 146p. (Acc. No.: T01145).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/10432
dc.description.statementofresponsibility	by Tom Glint Issac
dc.format.extent	xii, 146p.: hbk.; 30 cm
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	Deep Neural Networks (DNN)
dc.subject	Conventional Hardware Accelerators (CHA)
dc.subject	Processing In Memory (PIM)
dc.subject	Near Data Processors (NDP)
dc.subject	Artificial Intelligence
dc.title	Architecting fast and energy-efficient hardware accelerators for emerging ML workloads using hardware-software co-design
dc.type	Thesis
dc.contributor.department	Computer Science and Engineering
dc.description.degree	PhD