A Hardware-Software Co-Design platform to evaluate SNN workloads for ReRAM-based IMC

Abstract

Resistive random access memory (ReRAM) based analog in-memory-compute (IMC) coupled with spiking neural networks (SNN) offers a promising solution to implement efficient matrix multiplication. This work presents an ARM Cortex-based ReRAM IMC for rapid SNN workload evaluation. While the software flexibility and the scheduling are provided by the ARM processing system (PS), the programmable logic (PL) provides a scalable interface to the ReRAM array through mixed-signal digital-to-analog converters (DAC). A prototype system is presented using a Zynq 7000 SoC comprising an ARM PS and PL infrastructure. Custom 8x8 ReRAM array along with row and column DACs and leaky-integrate and fire (LIF) neurons are implemented to realize the end-to-end system. A use-case of a stashing-based MNIST classification task is demonstrated using the prototype system.