A neuromodulation-based spiking neural network using ReRAM array

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dc.contributor.author Shah, Nirmal
dc.contributor.author Sakhuja, Jayatika
dc.contributor.author Ganguly, Udayan
dc.contributor.author Lashkare, Sandip
dc.contributor.author Somappa, Laxmeesha
dc.coverage.spatial United Kingdom
dc.date.accessioned 2025-07-16T10:50:15Z
dc.date.available 2025-07-16T10:50:15Z
dc.date.issued 2025-05-25
dc.identifier.citation Shah, Nirmal; Sakhuja, Jayatika; Ganguly, Udayan; Lashkare, Sandip and Somappa, Laxmeesha, "A neuromodulation-based spiking neural network using ReRAM array", in the IEEE International Symposium on Circuits and Systems (ISCAS 2025), London, UK, May 25-28, 2025.
dc.identifier.uri https://doi.org/10.1109/ISCAS56072.2025.11044010
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/11649
dc.description.abstract This work proposes a neuromodulation-inspired spiking neural network using a ReRAM memory. A stashing-merging algorithm is realized to mimic the inherent neuromodulation in humans. While traditional pruning methods remove redundant parts of the network, stashing excludes well-trained neurons while training and restores all neurons at the end of training. This approach exhibits energy-efficient training in the context of a spiking neural network (SNN) since well-trained neurons can be easily identified using the spike count. The idea is validated using a ReRAM-based SNN with 10 conductance levels and performs close to a traditional artificial neural network (ANN) on an MNIST classification workload.
dc.description.statementofresponsibility by Nirmal Shah, Jayatika Sakhuja, Udayan Ganguly, Sandip Lashkare and Laxmeesha Somappa
dc.language.iso en_US
dc.publisher Institute of Electrical and Electronics Engineers (IEEE)
dc.subject Neuromodulation
dc.subject Neuromorphic computing
dc.subject Spiking neural networks
dc.subject ReRAM
dc.subject Stashing algorithm
dc.subject Neurons
dc.subject Synapse
dc.title A neuromodulation-based spiking neural network using ReRAM array
dc.type Conference Paper
dc.relation.journal IEEE International Symposium on Circuits and Systems (ISCAS 2025)


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