Comprehensive study of parasitic capacitance in CFETs: an analytical perspective

Abstract

This work presents a comprehensive study on parasitic capacitance and its corresponding analytical model for complementary field-effect transistor (CFET) devices. The model accounts for various capacitance components, including parallel plate, perpendicular and coplanar plate fringing, junction, separator, and offset capacitances between the gate and source/drain. Individual parasitic capacitance components are isolated using TCAD simulations by adjusting the geometrical and material properties of the device. The fringing capacitance components are modeled using the elliptical integral method, and the model effectively captures the significant contribution of separator capacitance (~20%) to the total parasitic capacitance. With only one fitting parameter, the model demonstrates high accuracy across different device structures. A comparative analysis with lateral nanosheet field-effect transistor (NsFET) devices highlights the impact of the stacked nFET-on-pFET architecture on parasitic capacitance overheads.