On the ESD Protection for 10V-Compliant Neural Stimulator in 65nm CMOS Technology

Abstract

Implantable biomedical circuits offer wide applications including the treatment of neurological disorders. To ensure reliability in terms of ESD (Electrostatic discharge) damage from fabrication, packaging, and user handling, ESD protection is required to protect the core circuit from any damage. A complete closed-loop neuromodulation SoC with on-site recording and digital core coupled with the cost necessitates the design to be implemented in a 65nm CMOS technology. Custom ESD protection has to be incorporated since the foundry-provided ESD cannot handle the high voltages required for faithful current stimulations. While existing stimulator designs in 65nm CMOS use implicit diodes of the driver stage as part of ESD protection, we show that this leads to coupling of the ESD design with the driver design, leading to suboptimal area and possible failure cases due to stress. This work proposes a 10 V compliant stimulator with an ESD protection circuit in± a 65 nm CMOS process verified for the HBM model using post-layout TLP simulations. This work also provides insights and details on the decoupling of the ESD design from the stimulator driver design to realize a low-footprint device.