| dc.contributor.author |
Likhitkar, Praful |
|
| dc.contributor.author |
Maheshwari, Navin |
|
| dc.contributor.author |
Lashkare, Sandip |
|
| dc.coverage.spatial |
Hong Kong |
|
| dc.date.accessioned |
2025-08-01T07:02:19Z |
|
| dc.date.available |
2025-08-01T07:02:19Z |
|
| dc.date.issued |
2025-03-09 |
|
| dc.identifier.citation |
Likhitkar, Praful; Maheshwari, Navin and Lashkare, Sandip, "Controlling the clamping voltage in punch-through diodes via N+ well and contact design for low voltage system level ESD protection", in the 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM 2025), HK, Mar. 09-12, 2025. |
|
| dc.identifier.uri |
https://doi.org/10.1109/EDTM61175.2025.11040750 |
|
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/11713 |
|
| dc.description.abstract |
A low voltage Electrostatic Discharge protection device is essential for low-voltage interfaces such as low-voltage MDIOs, Next-gen USB, and Thunderbolt interfaces. Here, a four-layer (n++p+p−n+) punch through diode is studied comprehensively, emphasizing lowering clamping voltage (Vclamp) by reducing dynamic resistance (RDYN). Further, two advanced designs with multi-contact & n+ well design are proposed to reduce the RDYN. The n+ well design lowers the RDYN by ∼30%, lowering the Vclamp and enhancing IC protection. |
|
| dc.description.statementofresponsibility |
by Praful Likhitkar, Navin Maheshwari and Sandip Lashkare |
|
| dc.language.iso |
en_US |
|
| dc.publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
|
| dc.subject |
Dynamic resistance |
|
| dc.subject |
Clamping voltage |
|
| dc.title |
Controlling the clamping voltage in punch-through diodes via N+ well and contact design for low voltage system level ESD protection |
|
| dc.type |
Conference Paper |
|
| dc.relation.journal |
9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM 2025) |
|