Inverse design of high power and high voltage LDMOS transistors using deep learning based sample-efficient surrogate model

Abstract

Device design using Machine Learning has been used in the semiconductor industry over the past ten years. However, the generation of the training data set for precise predictions using this technique remains burdensome. Addressing this, in this work, we propose eight sample-efficient techniques to train the Deep Neural Network (DNN) based surrogate models that emulate Technology Computer-Aided Design (TCAD). We showcase their efficacy by predicting off-state breakdown voltage (BVDS,off) and specific on-resistance (Rsp) of a Laterally Diffused Metal Oxide Semiconductor Field-effect Transistor (LDMOSFET). Our findings highlight the potential for 38% reduction in training dataset size while maintaining a strong predictive baseline accuracy. Specifically, the Diverse Representative-Query-by-Committee (DR-QBC) technique works best yielding 6.5% Euclidean Norm of Prediction Error (ENPE). We also demonstrate an inverse design framework by leveraging the same surrogate model with Differential Evolution (DE) and Bayesian Optimizer (BO). It mimics the role of a device design engineer by optimizing the values of structural parameters of the LDMOS transistors such that the desired BVDS,off is attained while minimizing Rsp.