Chip design for digital CIM architectures and efficient realization of 2D-DWT on Versal AI engine

dc.contributor.advisor	Mekie, Joycee
dc.contributor.author	Patel, Aashrey
dc.date.accessioned	2025-09-11T15:52:55Z
dc.date.available	2025-09-11T15:52:55Z
dc.date.issued	2025
dc.identifier.citation	Patel, Aashrey. (2025). Chip design for digital CIM architectures and efficient realization of 2D-DWT on Versal AI engine. Gandhinagar: Indian Institute of Technology Gandhinagar, 70p. (Acc. No.: T01423)
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/12018
dc.description.statementofresponsibility	by Aashrey Patel
dc.format.extent	xii, 70p.: hbk.: 30 cm
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	23210002
dc.subject	M. Tech
dc.subject	Electrical Engineering
dc.subject	Chip Design
dc.subject	Digital CIM Architecture
dc.subject	Versal AI Engine
dc.subject	2-D DWT
dc.subject	EDA Tools
dc.subject	Adaptive Compute Architectures
dc.title	Chip design for digital CIM architectures and efficient realization of 2D-DWT on Versal AI engine
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech.