ESD protection/clamping circuits for brain-machine interface

dc.contributor.advisor	Lashkare, Sandip
dc.contributor.author	Das, Tanay
dc.date.accessioned	2025-09-11T15:52:56Z
dc.date.available	2025-09-11T15:52:56Z
dc.date.issued	2025
dc.identifier.citation	Das, Tanay. (2025). ESD protection/clamping circuits for brain-machine interface. Gandhinagar: Indian Institute of Technology Gandhinagar, 66p. (Acc. No.: T01503)
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/12027
dc.description.statementofresponsibility	by Tanay Das
dc.format.extent	xxi, 66p.: hbk.: 30 cm
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	23210111
dc.subject	M. Tech
dc.subject	Electrical Engineering
dc.subject	Electrostatic Discharge (ESD)
dc.subject	Brain-Machine Interfaces (BMIs)
dc.subject	Integrated Circuits
dc.subject	Clamping Circuit
dc.subject	Neurostimulator
dc.subject	Neural Interface
dc.title	ESD protection/clamping circuits for brain-machine interface
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech.