Digital compute in memory chip design and validation

dc.contributor.advisor	Mekie, Joycee
dc.contributor.author	Kumar, Pawan
dc.date.accessioned	2025-09-11T15:52:56Z
dc.date.available	2025-09-11T15:52:56Z
dc.date.issued	2025
dc.identifier.citation	Kumar, Pawan. (2025). Digital compute in memory chip design and validation. Gandhinagar: Indian Institute of Technology Gandhinagar, 59p. (Acc. No.: T01532)
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/12035
dc.description.statementofresponsibility	by Pawan Kumar
dc.format.extent	x, 59p.: hbk.: 30 cm
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	23250028
dc.subject	M. Tech
dc.subject	Electrical Engineering
dc.subject	Integrated Circuits
dc.subject	Artificial Inteligence
dc.subject	Internet of Things
dc.subject	Graphic Data System
dc.subject	Application-Specific Integrated Circuits (ASICs)
dc.subject	CMOS Technology
dc.title	Digital compute in memory chip design and validation
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech.