Analysis of Gate Leakage Current in High-k Metal Gate MOS Transistors

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dc.contributor.advisor Mohapatra, Nihar Ranjan Ganeriwala, Mohit D. 2015-08-31T17:36:06Z 2015-08-31T17:36:06Z 2015
dc.identifier.citation Ganeriwala, Mohit D., (2015). Analysis of Gate Leakage Current in High-k Metal Gate MOS Transistors, (M. Tech. Dissertation).'Indian Institute of Technology, Ganadhinagar, pp. 62 (Acc No: T00079) en_US
dc.description.abstract "Increased power dissipation is one of the major issue for today’s chip designers. Gate leakage across the gate dielectric being one of the major component leading to power dissipation in circuits it is necessary to have its clear understanding. Due to distinctive properties of HfO2 dielectric, used in advance CMOS devices, the gate current through it is noticeably different from that of the conventional SiO2 dielectric. Literature reports extensive work to understand the gate current mechanism through HfO2 dielectric. However, these studies are either restrictive in terms of the applied bias or the type of MOS transistor. They also do not elaborate on the reasons for change in leakage mechanisms with change in gate voltages. Thus the gate current mechanism through this HfO2 dielectric is still controversial. This work analyses gate current of both nMOS and pMOS transistors with HfO2 dielectric gate stack. Using measurement and simulation studies we presents a theory which could consistently explains the gate leakage for the entire biasing range of both the MOS transistors. This theory also explains the observed temperature dependency shown by the gate current. The gate leakage is shown to be dependent on oxide traps which are generated due to large number of positively charge oxygen vacancies in HfO2. Also the change in energy level of these traps is shown to be responsible for change in leakage mechanism. Further it was shown for the first time in this work that the gate current is anomalously dependent on the width of the devices. The theory presented in this work explains this anomalous width dependency and it is attributed to the annihilation of positively charge oxygen vacancies at the corner of the activegate overlap region." en_US
dc.description.statementofresponsibility by Mohit D. Ganeriwala
dc.format.extent 62p;col.;ill.;28 cm. + 1 CD-RAM
dc.language.iso en_US en_US
dc.publisher Indian Institute of Technology, Ganadhinagar en_US
dc.subject Gate leakage en_US
dc.subject HfO2 en_US
dc.subject CMOS devices en_US
dc.subject Moores law, en_US
dc.subject MOS transistor en_US
dc.title Analysis of Gate Leakage Current in High-k Metal Gate MOS Transistors en_US
dc.type Thesis en_US
dc.contributor.department Electrical Engineering M.Tech.

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