Analog circuit synthesis and application

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dc.contributor.advisor Mohapatra, Nihar Venkat Ramakrishna, Saripalli 2017-03-23T09:59:14Z 2017-03-23T09:59:14Z 2016
dc.identifier.citation Saripali, V. (2016). Analog circuit synthesis and application. Indian Institute of Technology,pp. 82. (Acc No: T00186) en_US
dc.description.abstract The analog circuit sizing can be viewed as a constrained optimization problem. Evolutionary algorithms like genetic algorithm and simulated annealing are generally used to solve the analog circuit sizing problem. In this work a hybrid approach consisting of an evolutionary algorithm and a local search algorithm is used to solve the problem of analog circuit sizing. Circuits ranging from Common Source Amplifier to Telescopic Amplifiers have been designed. A LUT based simulator is also developed so that analog circuits can be designed using the CMOS technology nodes for which compact models are not available. Sub-45nm CMOS technologies with high- K gate dielectrics and metal gate (HKMG) stacks show improvement in trans-conductance (g) and intrinsic gain (gm ro) for narrow width transistors. The improvement in gm should improve the performance of analog circuits. For example, the gain should should be higher at same power dissipation and the power dissipated should be low at same gain when narrow width transistors are used in design. In this work this fact is verified using the LUT and optimizer approach. It is shown that the common source amplifier gain is improved by v 35% and cascoded amplifier gain is improved by v 65 % when the design is done using narrow width transistors. The similar behaviour is observed for all gate length. en_US
dc.description.statementofresponsibility by Venkat Saripali
dc.format.extent 82 p.; ill. : 30 cm+.
dc.language.iso en_US en_US
dc.publisher Indian Institute of Technology Gandhinagar en_US
dc.title Analog circuit synthesis and application en_US
dc.type Thesis en_US
dc.contributor.department Electrical Engineering M.Tech.

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