Effect of device dimensions, layout and pre-gate carbon implant on hot carrier induced degradation in HKMG nMOS transistors

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dc.contributor.author Duhan, Pardeep
dc.contributor.author Rao, V. Ramgopal
dc.contributor.author Mohapatra, Nihar Ranjan
dc.date.accessioned 2020-08-07T14:26:29Z
dc.date.available 2020-08-07T14:26:29Z
dc.date.issued 2020-07
dc.identifier.citation Duhan, Pardeep; Rao, V. Ramgopal and Mohapatra, Nihar Ranjan, “Effect of device dimensions, layout and pre-gate carbon implant on hot carrier induced degradation in HKMG nMOS transistors”, IEEE Transactions on Device and Materials Reliability, DOI: 10.1109/TDMR.2020.3007553, vol. 20, no. 3, pp. 555-561, Jul. 2020. en_US
dc.identifier.issn 1530-4388
dc.identifier.uri http://dx.doi.org/10.1109/TDMR.2020.3007553
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/5595
dc.description.abstract The hot carrier (HC) induced degradation has become a major concern in advanced CMOS technologies because of non-scalable VDD. In this work, we have shown that the HC induced degradation in gate-first HKMG nMOS transistors can be modulated by optimizing the device width, lanthanum capping layer thickness, and pre-gate carbon (C) implant. The physics responsible for these observations are investigated and attributed to the reduction in the number of defects (traps) in hafnium oxide (HfO2) and reduction in carrier injection into these defects. It is also shown that the HC performance of these transistors could be further improved by increasing the active-to-active spacing.
dc.description.statementofresponsibility by Pardeep Duhan, V. Ramgopal Rao and Nihar R. Mohapatra
dc.language.iso en_US en_US
dc.publisher Institute of Electrical and Electronics Engineers en_US
dc.subject Device scaling en_US
dc.subject channel width en_US
dc.subject gate current en_US
dc.subject Hafnium oxide (HfO2) en_US
dc.subject high-k metal gate (HKMG) en_US
dc.subject hot carrier injection en_US
dc.subject Lanthanum (La) capping layer en_US
dc.subject dipole en_US
dc.subject threshold voltage. en_US
dc.title Effect of device dimensions, layout and pre-gate carbon implant on hot carrier induced degradation in HKMG nMOS transistors en_US
dc.type Article en_US
dc.relation.journal IEEE Transactions on Device and Materials Reliability


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