Process induced threshold voltage variability in Ultra-Thin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FDSOI) transistors

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dc.contributor.advisor Mohapatra, Nihar Ranjan
dc.contributor.author Verma, Ankit Kumar
dc.date.accessioned 2021-10-27T14:12:41Z
dc.date.available 2021-10-27T14:12:41Z
dc.date.issued 2021
dc.identifier.citation Verma, Ankit Kumar (2021). Process induced threshold voltage variability in Ultra-Thin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FDSOI) transistors. Gandhinagar: Indian Institute of Technology Gandhinagar, 38p. (Acc. No.: T00846).
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/7137
dc.description.statementofresponsibility by Ankit Kumar Verma
dc.format.extent viii, 38 p.: ill.; 30 cm.
dc.language.iso en_US
dc.publisher Indian Institute of Technology Gandhinagar
dc.title Process induced threshold voltage variability in Ultra-Thin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FDSOI) transistors
dc.type Thesis
dc.contributor.department Electrical Engineering
dc.description.degree M.Tech


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