System-level analysis of dual node upset tolerant flip-flops

dc.contributor.advisor	Mekie, Joycee
dc.contributor.author	Agarwal, Ayush
dc.date.accessioned	2021-10-27T14:12:41Z
dc.date.available	2021-10-27T14:12:41Z
dc.date.issued	2021
dc.identifier.citation	Agarwal, Ayush (2021). System-level analysis of dual node upset tolerant flip-flops. Gandhinagar: Indian Institute of Technology Gandhinagar, 81p. (Acc. No.: T00858).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/7149
dc.description.statementofresponsibility	by Ayush Agarwal
dc.format.extent	xiii, 81p.: ill.; hbk.; 30 cm.
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	19210072
dc.subject	Circuits and Systems
dc.subject	CMOS technology
dc.subject	Microelectronics
dc.subject	Nuclear Science
dc.subject	Adaptive Hardware
dc.title	System-level analysis of dual node upset tolerant flip-flops
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech