A physics-based compact model to capture cryogenic behavior of LDMOS transistors

Abstract

In this work, a detailed characterization of lateral DMOS transistors in the cryogenic regime is carried out. It is shown that carrier freeze-out in the drift region is responsible for increased ON-resistance for temperatures lower than a transition temperature, which is independent of device dimensions. The carrier freeze-out affects the operation of laterally diffused MOS (LDMOS) transistors in the linear region but not in the saturation region due to field-assisted ionization. A peak behavior in output conductance is also observed at cryogenic temperatures. The physics behind these observed anomalous behaviors is studied in detail and modeled. The industry-standard HiSIM_HV2 model is augmented with new equations to extend the model accuracy to 77 K. The accuracy of the model is verified with the data measured from LDMOS transistors with different dimensions. The model accurately captures the device behavior in the 77-300 K temperature range and demonstrates excellent scalability.