The present disclosure relates to the field of power semiconductor devices and envisages a Source side underlap LDMOS (SU LDMOS) transistor and a method of fabricating SU LDMOS. The SU LDMOS transistor includes a Source-, a Drain- and a Gate region. The fabrication method comprises the steps of Shallow-Trench Isolation (STI), Well implantation, Silicon dioxide (SiO2) growth, poly-Silicon deposition and patterning (Gate-stack formation), drift region implantation, Spacer formation, S/D Implantation and Salicidation followed by Back-end of Line (BEOL). The method forms an underlap region between the Source and Gate regions, that introduces a resistance (Rx) at the Source end. The underlap region facilitates elimination of quasi-saturation and impact-ionization issues and improvement in on-state breakdown voltage (BVDS,on) of said transistor, safe operating area, transistor�s output conductance (gds), intrinsic gain (gm/gds), and cut-off frequency (fT).