Title
A low voltage electrostatic discharge protection device
Journal
Indian Patent Office (IPO)
Date Issued
2024-07-01
Author(s)
Abstract
The present disclosure relates to an electrostatic discharge protection (ESD) device (100). The device (100) comprises a first highly doped n-type region (102a), a second highly doped n-type region (102b), a highly doped p-type region (104) and a pair of intrinsic regions (106a) and (106b). The highly doped p-type region (104) is disposed between the first and second highly doped n-type regions. The pair of intrinsic regions (106a) and (106b) is disposed between the n-type regions (102a) and (102b) and the p-type region (104). The first and second n-type semiconductor regions (102a) and (102b), the intrinsic semiconductor regions (106a) and (106b), and the p-type semiconductor region (104) is collectively form a N?�I�P?�I�N? (NIPIN) structure. The intrinsic regions (106) together with the p-type region define a barrier region characterized by a triangular energy band profile under equilibrium.
Subjects
ELECTRONICS
