Design-Analysis of CNTFET-Based Energy Efficient Ternary Logic Gates

Carbon nanotube field-effect transistors (CNTFETs) show great potential for designing multiple-valued logic (MVL) gates due to their exceptional electrical properties, such as the ability to control threshold voltage by adjusting the chirality of the carbon nanotube. This makes CNTFETs stand out as promising candidates when compared to conventional and other emerging device technologies. MVL represents more data or information than binary logic using the same number of logic bits. Energy-efficient ternary logic gates like standard ternary inverter (STI), ternary NAND (TNAND), and ternary NOR (TNOR) gates have been proposed. The use of transmission gates, pass transistors, and two power supplies has led to a significant reduction in power consumption in the proposed circuits. The power-delay-product (PDP) for the proposed STI, TNAND, and TNOR is reduced by 70.38%, 77.27%, and 39.8%, respectively, compared to the lowest PDP among the designs being evaluated.