High performance rediation hardened random access and content addressable memory designs
Source
Indian Institute of Technology, Gandhinagar
Date Issued
2019-01-01
Author(s)
Barma, Abhishek
Subjects
17210024
Electrical Engineering
Robust Circuits
Particle Strike Immunity
Dual Port-Dual Interlocked Structure
Mixed Vt Ternary Content Addressable Memory
