Physics-based Scalable Compact Model for Terminal Charge, Intrinsic Capacitance and Drain Current in Nanosheet FETs
Source
8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM 2024)
Date Issued
2024-01-01
Author(s)
Abstract
This work presents a physics-based SPICE compatible model for Nanosheet FETs, which provides explicit expressions for the drain current, terminal charges and intrinsic capacitances. The drain current model is based on the drift-diffusion formalism for carrier transport. The terminal charge and intrinsic capacitance models are calculated by adopting the Ward-Dutton linear charge partition scheme that guarantees charge conservation. The model uses the novel bottom-up approach to calculate the terminal charges, uses very few empirical parameters and is accurate across device dimensions and bias conditions.
Subjects
bottom-up scalable compact model | nanosheet FET | quantum confinement | terminal charges | Ward-Dutton
