Process-Performance Variability Modeling of Inner Spacer Etch in GAA FETs

This work presents a robust machine learning (ML) framework for modeling the inner spacer etch process and its impact on electrical behavior in gate-all-around (GAA) FETs. Leveraging an in-house Process Monte Carlo (PMC) simulator, the etch front evolution under diverse process conditions is simulated. Gaussian Process Regression (GPR) demonstrates superior accuracy (98.5%) in modeling inner spacer etch process. Artificial Neural Networks (ANNs) are employed to map inner spacer etch geometric variations to device current characteristics with 98.2% accuracy. The proposed ML pipeline establishes a direct process-to-device link, enabling accurate assessment of electrical performance variations, and paving the way for data-driven process-performance co-optimization in advanced transistor technologies.