Impact of Memory Parameters on Sensitivity Margin of Analog-to-Digital Converter Limiting Neural Network Density

In-memory computing (IMC) is a computing paradigm inspired by the brain, implemented on an interconnected network of computing (neurons) and reconfigurable memory (synapse) elements that can perform multiply and accumulate (MAC) operations in the memory, thereby improving latency and reduce power consumption, mitigating the von Neumann bottleneck. Resistive memory is an emerging technology that can act as computing and memory elements employed in crossbar arrays to offer intrinsic MAC functionality. The analog MAC output is quantized to digital values using ADC for further computations in different applications. Therefore, the accuracy of ADC is crucial. This paper examines the impact and constraints of RRAM parameters on neural network density (n), including conductance ratio (k), memory window (MW), and device variability (Ivar), by analyzing the limit on ADC sensitivity margin (SM). First, we identify the critical SM point in the MAC output. Next, at the device level, we experimentally show the impact of k and Ivar on MW, which essentially defines the SM of an ADC. MW decreases by 10x with 10x smaller k and 30% Ivar. At the array MAC (column output) level, for a given k the limit on n decreases. Further, we empirically investigated that the tolerance to device variability can be achieved by increasing k. The enhancement can be realized by amplifying the MAC output multiplier solution that has been demonstrated to improve the device limit and design space requirements.