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  4. Dissecting Parasitic Capacitance in Nanosheet FETs: An Analytical Perspective
 
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Dissecting Parasitic Capacitance in Nanosheet FETs: An Analytical Perspective

Author(s)
A.K., Singh, Aishwarya K.
O., Maheshwari, Om
N.R., Mohapatra, Nihar Ranjan  
DOI
10.1109/EDTM58488.2024.10512230
Abstract
This work presents an approach to extract and analytically model the parasitic capacitance components in Nanosheet FETs. Along with parallel and fringing components, the junction capacitance which is a significant contributor to the total parasitic capacitance is accurately modeled for the first time. The fringing parasitic capacitance components are modeled using the Elliptical Integral Method. The model uses only one fitting parameter and is accurate across the device structural variations with only 1.2% error. � 2024 Elsevier B.V., All rights reserved.
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URI
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85193249606&doi=10.1109%2FEDTM58488.2024.10512230&partnerID=40&md5=b9284944d75d3b2c9b974cdc98598e87
https://d8.irins.org/handle/IITG2025/29353
Keywords
Capacitance
Elliptical integral method
Elliptical integrals
Fitting parameters
Integral method
Junction capacitances
Model use
Nanosheet FET
Parasitics capacitance
Structural variations
Nanosheets
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