Memory bottlenecks in Quantum simulation: cache contention and adaptive allocation policy

Quantum simulation on classical hardware remains essential for validating quantum algorithms until large-scale quantum processors become practical. Because classical systems lack the computational advantages of quantum hardware, simulator performance is strongly influenced by how these workloads interact with the underlying architecture. This motivates a deeper system-level analysis to understand performance behavior, memory demands, and architectural bottlenecks in quantum simulation. In this work, we perform a comprehensive evaluation of widely used quantum simulators, measuring execution time, memory usage, last-level cache (LLC) miss rates, page faults, and IPC. Our analysis shows that all simulators are strongly memory-bound, with consistently high LLC miss rate and low instructions per cycle (IPC) values. To further understand this bottleneck, we study cache sensitivity using varying LLC way-allocation policies under disjoint and overlapping cache way configurations. We observe that the choice of allocation policy can reduce LLC miss rates by up to 7.5%, and neither disjoint nor overlapping allocations are universally optimal.