Controlling the Clamping Voltage in Punch-Through Diodes via N+ Well and Contact Design for Low Voltage System Level ESD Protection

A low voltage Electrostatic Discharge protection device is essential for low-voltage interfaces such as low-voltage MDIOs, Next-gen USB, and Thunderbolt interfaces. Here, a four-layer (n⁺⁺p⁺p^-n⁺) punch through diode is studied comprehensively, emphasizing lowering clamping voltage (Vclamp) by reducing dynamic resistance (RDYN). Further, two advanced designs with multi-contact & n+ well design are proposed to reduce the RDYN. The n+ well design lowers the RDYN by ~ 30%, lowering the Vclamp and enhancing IC protection.