Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS Transistors

This paper analyzes and models the stress over layer induced threshold voltage (VT) shift observed in high-K metal gate (HKMG) nMOS transistors. It is shown that the conventional in-plane uniaxial strain based VT shift model cannot explain the large VT shift observed in HKMG MOS transistors. A VT shift model considering both the in-plane longitudinal and out-of-plane transverse stress component is proposed. The accuracy of the proposed model is verified by comparing it with the experimental data obtained from the transistor fabricated using 28nm HKMG CMOS technology. The new model, unlike the earlier models, successfully predicts the stress over layer induced VT shift in HKMG nMOS transistors within 5% for all gate lengths.