Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA

Source
Proceedings 2023 IEEE International Symposium on Performance Analysis of Systems and Software Ispass 2023
Date Issued
2023-01-01
Author(s)
Glint, Tom
Gupta, Aryan
Giftson, Daniel
Shah, Gaurav
Patel, Vrajesh
Chudasama, Ruchit
More, Sukanya
DOI
Abstract
Due to their flexibility, FPGAs are used to deploy Deep Neural Network Accelerators (DA) at various compute locations such as servers and edge computes. In this work, we show the impact of choosing architectural parameters on performance metrics for SOTA DA implemented on FPGA, and the optimal design point for maximum compute throughput.
Unpaywall
URI
Subjects
DNN Accelerator | FPGA