ESD protection with Sub-3 Ω dynamic resistance for neuromodulation system-on-chip

Implantable neurostimulators are critical for treating neurological disorders and require compact CMOS systems with long-term reliability. Electrostatic discharge (ESD) can damage thin oxide layers in the CMOS and can cause significant damage to systems. Conventional ESD protection circuits, such as clamp-based schemes with implicit or explicit diodes, are practical but require considerable area and complexity. Conversely, simpler protection architectures are more suitable for high-voltage neural interfaces, for which area and robustness are the key requirements. The major challenge is to achieve efficient ESD protection while ensuring operational safety and low layout area. This paper presents a compact back-to-back diode–based ESD protection design for neurostimulators in 65 nm CMOS technology, primarily targeting HBM-level ESD protection. The circuit has also been tested for CDM-level robustness; however, the main focus of this work remains on achieving reliable HBM performance. The proposed back-to-back diode design reduces clamping voltage by ~53% and dynamic resistance by ~89% when compared with implicit clamps while meeting the normal voltage operation range. In addition, the proposed design reduces dynamic resistance by more than 92% compared to the typical foundry design. As a result, ESD protection can be decoupled from stimulator drivers, allowing for more modular and area-efficient H-bridge designs. This simplifies the layout, eliminates the need for clamping transistors, and provides robust bidirectional ESD protection. Our work proposes a scalable ESD strategy appropriate for next-generation implantable SoC-based biomedical devices by addressing electrical and physical constraints.