Evaluating the Scaling Effects on Synchronizers and Global Interconnects in Multicore SoCs

Aggressive technology scaling enables the implementation of multicore SoCs (Systems on Chip) for achieving better performance, but it also poses a great challenge due to various bottlenecks varying from architecture level, design level, gate level to interconnect level. This thesis evaluates the scaling effects on two issues- Global Interconnect Delay issue and Metastability issue during Synchronization. The critical paths of a chip are made of global interconnects which impact the chip performance. These critical paths

need to be identified and their delays need to be optimized ahead of the HLD (High Level Design Phase) for the fastest timing closure. This puts the EDA (Electronic Design Automation) community in a challenging scenario as the existing CAD (Computer Aided Design) tools do not support this analysis. This thesis proposes a methodology for synthesizing the critical paths and automating the design with RTL Compilers.

Due to the homogeneous and heterogeneous clock regions in multicore SoCs, there is a need for synchronizing the data passing between these clocking domains and hence study of synchronizers is important. This thesis also focuses on evaluating the scaling effects on synchronizers and study of metastability parameters with PVT (Process, Voltage and Temperature) variations. It is found that synchronizer performance degrades due to technology scaling. Detailed statistical simulations and an accurate small signal analysis is done to confirm the above results. The observations match with the measurement trends proposed in the past. This thesis provides an intuition for the reported measurement trends from the process simulations.