Design of ESD protection with on-chip diodes for 65nm CMOS high voltage neurostimulators

ESD protection is a critical requirement for high-voltage biomedical integrated circuits, particularly implantable neurostimulators, where device failure can affect patient safety. The clamp-based protection circuits used in conventional ESD protection often exceed layout space constraints and suffer from high clamping voltages and dynamic resistance. Our work presents a compact and efficient ESD protection scheme for 65 nm CMOS neurostimulators using back-to-back diodes. A breakdown voltage of 10.5 V is achieved, clamping voltages do not exceed 16 V, and the proposed design fits within the circuit-under-pad area (CUP). In comparison to standard diode designs, there is a 92.35 % reduction in dynamic resistance and a 58.3% reduction in the Clamp Voltage (VClamp). By eliminating control circuitry and improving ESD clamping performance, this technique enables robust protection for high-density biomedical SoCs.