Overcoming Silicon MOSFET Limitations with Chirality-Engineered CNTFETs: A Ternary Half Adder Demonstration for Next-Generation Nanoelectronics

The implementation of multi-valued logic (MVL) systems becomes increasingly difficult as silicon MOSFETs reach their scaling limits due to fixed threshold voltages and worsened short-channel effects. Carbon nanotube field-effect transistors (CNTFETs) present a compelling alternative, exhibiting ballistic charge transport characteristics and chirality-dependent threshold voltage tunability—an essential property for realizing efficient MVL implementations. Comprehensive device characterization using HSPICE demonstrates the superior electrical characteristics of CNTFETs over conventional MOSFETs. The ON current (ION) of the n-type CNTFET is approximately 2.66 times greater than that of its n-type MOSFET counterpart, whereas its OFF current (IOFF), exceeds by more than 16.1 times. For the p-type devices, the CNTFET exhibits an ION over 2.866 times higher than that of the p-type MOSFET, while its IOFF exceeds by more than 12.4 times. The Ion/Ioff ratio for n-type and p-type CNTFETs is 42.9 and 36.7 times higher, respectively, compared to their MOSFET counterparts. Utilizing chirality engineering, the CNTFETs are specifically adjusted to implement the ternary logic. This work delves into the chirality engineering of CNTFETs, utilizing (19,0) and (10,0) vectors, to develop an optimized novel high-performance and robust CNTFET-based ternary half adder (THA). The proposed 38-transistor architecture employs a dual-supply voltage scheme and eliminates conventional gates and multiplexers, resulting in a compact 4.6 µm² layout. Simulations using the 32-nm Stanford CNTFET model reveal 13.9% lower power consumption (0.940 µW), 12.4% faster delay (50.165 ps), and 25.4% better power-delay product (0.047 pJ) than the best existing THA design. The design also demonstrates strong resilience to parametric variations, making it a promising solution for low-power, high-speed arithmetic units in energy-constrained nanoelectronics systems.