Abstract:
custom Electrostatic Discharge (ESD) protection circuit is essential for the reliability of 10−V neurostimulators implemented in a standard low-voltage CMOS process. The typical foundry-provided ESD diode cannot protect the ESD event without compromising on area. Here, we propose a custom ESD protection design in 65 nm CMOS technology within the given area of 57×72μm2, limited to pad size. The dynamic resistance (Rdyn) of the proposed design is 3Ω which is >10X lower as compared to the foundry-provided design (31.93Ω) providing substantially lower clamping voltage (∼12V) than the oxide breakdown limit (16V).