| dc.contributor.author |
Das, Tanay |
|
| dc.contributor.author |
Ahmad, Naef |
|
| dc.contributor.author |
Somappa, Laxmeesha |
|
| dc.contributor.author |
Lashkare, Sandip |
|
| dc.coverage.spatial |
Hong Kong |
|
| dc.date.accessioned |
2025-08-01T07:02:19Z |
|
| dc.date.available |
2025-08-01T07:02:19Z |
|
| dc.date.issued |
2025-03-09 |
|
| dc.identifier.citation |
Das, Tanay; Ahmad, Naef; Somappa, Laxmeesha and Lashkare, Sandip, "Enhanced ESD protection techniques for 10V neurostimulator circuits in 65nm CMOS technology", in the 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM 2025), HK, Mar. 09-12, 2025. |
|
| dc.identifier.uri |
https://doi.org/10.1109/EDTM61175.2025.11041318 |
|
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/11710 |
|
| dc.description.abstract |
custom Electrostatic Discharge (ESD) protection circuit is essential for the reliability of 10−V neurostimulators implemented in a standard low-voltage CMOS process. The typical foundry-provided ESD diode cannot protect the ESD event without compromising on area. Here, we propose a custom ESD protection design in 65 nm CMOS technology within the given area of 57×72μm2, limited to pad size. The dynamic resistance (Rdyn) of the proposed design is 3Ω which is >10X lower as compared to the foundry-provided design (31.93Ω) providing substantially lower clamping voltage (∼12V) than the oxide breakdown limit (16V). |
|
| dc.description.statementofresponsibility |
by Tanay Das, Naef Ahmad, Laxmeesha Somappa and Sandip Lashkare |
|
| dc.language.iso |
en_US |
|
| dc.publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
|
| dc.subject |
Dynamic resistance |
|
| dc.subject |
Electrostatic discharge |
|
| dc.title |
Enhanced ESD protection techniques for 10V neurostimulator circuits in 65nm CMOS technology |
|
| dc.type |
Conference Paper |
|
| dc.relation.journal |
9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM 2025) |
|