Design of 61 GHz phase locked loop in 65 nm CMOS technology for 6G wireless communication systems

dc.contributor.advisor	Agarwal, Tarun Kumar
dc.contributor.author	Kumari, Sapna
dc.date.accessioned	2025-09-11T15:52:56Z
dc.date.available	2025-09-11T15:52:56Z
dc.date.issued	2025
dc.identifier.citation	Kumari, Sapna. (2025). Design of 61 GHz phase locked loop in 65 nm CMOS technology for 6G wireless communication systems. Gandhinagar: Indian Institute of Technology Gandhinagar, 57p. (Acc. No.: T01536)
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/12036
dc.description.statementofresponsibility	by Sapna Kumari
dc.format.extent	v, 57p.: hbk.: 30 cm
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	23250038
dc.subject	M. Tech
dc.subject	Electrical Engineering
dc.subject	Integer-N
dc.subject	CMOS
dc.subject	Phase Locked Loop
dc.subject	Phase-Detector
dc.subject	Signal Frequency Divider
dc.subject	Wireless Communication
dc.title	Design of 61 GHz phase locked loop in 65 nm CMOS technology for 6G wireless communication systems
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech.