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  5. Parasitic capacitance analysis in tapered CFET devices for advanced technology nodes
 
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Parasitic capacitance analysis in tapered CFET devices for advanced technology nodes

Source
IEEE 7th International Conference on Emerging Electronics (ICEE 2025)
Date Issued
2025-12-13
Author(s)
Pal, Jaisingh
Mohapatra, Nihar Ranjan  
DOI
10.1109/ICEE67165.2025.11409786
URI
https://repository.iitgn.ac.in/handle/IITG2025/34824
Subjects
CFET
Parasitic capacitance
Taper angle
Process variation
3D TCAD
Elliptical integral method
Trapezoid
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