Investigating the analog performace of FinFETs in sub-10nm Wfin regime by analyzing the drain saturation voltage (VDS,SAT )
Source
Indian Institute of Technology, Gandhinagar
Date Issued
2020-01-01
Author(s)
Jain, Shubham
Subjects
18210080
Electrical Engineering
TCAD Simulation
RF parameters
Semiconductor Devices
CMOS Technology