Scalable edge contacts to two-dimensional semiconductors

Contact engineering for two-dimensional (2D) field effect transistors (FETs) has advanced rapidly, with near-quantum-limit contact resistances (R_C) now reported for top contacts formed by physical vapor deposition (PVD) techniques. However, top contacts are inherently scaling-unfriendly because they are limited by transfer-length (L_T). As contact length (L_C) shrinks below L_T, current crowding inflates R_C, constraining footprint scaling. Furthermore, this contact geometry is also ill-matched to stacked nanosheet and gate all around (GAA) transistor technology, which demands tier-addressable, minimal-footprint contacts, i.e., edge contacts. Early reports on edge contact to 2D materials involve PVD approaches with minimal control on the contact/2D interface. Here we introduce a scalable, chemistry-defined edge-contact platform based on atomic layer deposition (ALD) of metallic transition-metal chalcogenides, which exploits the intrinsic reactivity contrast between inert 2D basal planes and under-coordinated edges. Using ALD-grown TiS2 as a prototype, we form conformal edge contacts to wafer-scale monolayer MoS2, WS2, MoSe2 and WSe2, as well as to a multi-tier MoS2 nanosheet stack, illustrating natural compatibility with 2D GAA geometries. For TiS2–MoS2 edge contacts we obtain a contact resistance of ~130 kΩ·µm, consistent with a Schottky barrier of ~0.43 eV, and establish wafer-scale reproducibility through statistics on 100 n-type and 100 p-type devices. First-principles quantum-transport calculations both reproduce the measured barriers and identify alternative ALD-compatible metals that approach near-ohmic edge injection, while revealing that mode matching and edge termination are as critical as band alignment. Finally, complementary inverters assembled from MoS2/WSe2 edge-contacted FETs demonstrate functional logic with well-defined gain, noise margins and static power, positioning ALD-engineered edge contacts as a practical route to high-density 2D CMOS and 3D-integrated nanosheet technologies.