Development of an analytical model of drain current for junction less GAA MOSFET including source/drain resistance

Fabrication of devices in deca nanometer regime suffers from several limitations as the devices are being scaled so that the speed and transistor density can be increased. This has led to a series of innovative techniques by the industry as well as academia. Depletion regions formed in association with the p-n junctions is one of the restrictive factors in scaling short channel devices in case of junction-based (JB) metal-oxide-semiconductor feld-effect transistors (MOSFETs). This has led to several short channel effects (SCEs). Recently, novel MOSFET structures have been developed that are devoid of p-n junctions and have also been successfully fabricated. These devices are named “junction less transistors (JLTs)”. MOSFETs employing gate-all-around (GAA) architecture have been reported as an ultimate structure in silicon integrated circuits (ICs). In this paper, we have developed an analytical drain current model for short channel GAA JLT, including source (S)/drain (D) series resistance, which is also one of the important parameters when devices with short channel are fabricated. We have obtained the potential distribution profle using Poisson’s equation. It was then used for obtaining the model for drain current. The validation of the model has been obtained with both the simulation as well as experimental results. We have further analyzed the effect of S/D resistance on the drain current for different device parameters.